A typical analog-to-digital converter (ADC) circuit chops an input analog signal by swapping a positive and a negative polarity of a differential signal at an input of the ADC periodically to reduce or eliminate an effective DC voltage bias (e.g., voltage offset) at the analog input. Chopping is typically periodic with both a non-inverted phase (Chop0) and an inverted phase (Chop1) having a fixed and equal sampling time. By summing the two previous chop phase analog to digital conversion results at the end of each switch inversion, voltage offset contributions through the ADC (chopped path), may be cancelled. This summing is typically done as part of the digital filtering in a delta-sigma ADC architecture.
A consequence of chopping is that a settling time of a filter within the ADC may be increased (e.g., typically doubled). A further consequence of chopping is that once the filter has settled, the effective settled throughput may be reduced by typically a factor N where N represents the order of the digital filter, thereby reducing an effective data throughput of the ADC accordingly.